A 2.7-kW, 29-MHz class-E/F/sub odd/ amplifier with a distributed active transformer

A Class-E/Fodd high power amplifier (PA) using the distributed active transformer (DAT) is demonstrated at 29MHz. The DAT combines the output power from four VDMOS push-pull pairs. The zero voltage switching (ZVS) condition is investigated and modified for the Class-E/Fodd amplifier with a non-ideal output transformer. All lumped elements including the DAT and the transistor package are modeled and optimized to achieve the ZVS condition and the high drain efficiency. The PA exhibits 2.7kW output power with 79% drain efficiency and 18dB gain at 29MHz

Analysis and elimination of hysteresis and noisy precursors in power amplifiers

Power amplifiers (PAs) often exhibit instabilities leading to frequency division by two or oscillations at incommensurate frequencies. This undesired behavior can be detected through a large-signal stability analysis of the solution. However, other commonly observed phenomena are still difficult to predict and eliminate. In this paper, the anomalous behavior observed in a Class-E PA is analyzed in detail. It involves hysteresis in the power-transfer curve, oscillation, and noisy precursors. The precursors are pronounced bumps in the power spectrum due to noise amplification under a small stability margin. The correction of the amplifier performance has required the development of a new technique for the elimination of the hysteresis. Instead of a trial-and-error procedure, this technique, of general application to circuit design, makes use of bifurcation concepts to suppress the hysteresis phenomenon through a single simulation on harmonic-balance software. Another objective has been the investigation of the circuit characteristics that make the noisy precursors observable in practical circuits and a technique has been derived for their elimination from the amplifier output spectrum. All the different techniques have been experimentally validated

Nonlinear Design Technique for High-Power Switching-Mode Oscillators

A simple nonlinear technique for the design of high-efficiency and high-power switching-mode oscillators is presented. It combines existing quasi-nonlinear methods and the use of an auxiliary generator (AG) in harmonic balance. The AG enables the oscillator optimization to achieve high output power and dc-to-RF conversion efficiency without affecting the oscillation frequency. It also imposes a sufficient drive on the transistor to enable the switching-mode operation with high efficiency. Using this AG, constant-power and constant-efficiency contour plots are traced in order to determine the optimum element values. The oscillation startup condition and the steady-state stability are analyzed with the pole-zero identification technique. The influence of the gate bias on the output power, efficiency, and stability is also investigated. A class-E oscillator is demonstrated using the proposed technique. The oscillator exhibits 75 W with 67% efficiency at 410 MHz

A 6-to-18 GHz tunable concurrent dual-band receiver front end for scalable phased arrays in 130nm CMOS

This paper presents a study and design of tunable concurrent dual-band receiver. Different system architectures and building blocks have been compared and analyzed. A tunable concurrent dual-band receiver front end has then been fabricated and characterized. It operates across a tri-tave 6-18 GHz bandwidth with a nominal 17-25 dB conversion gain, worst-case -15 dBm IIP3, and worst-case -24.5 dBm ICP 1 dB

Global stability analysis and stabilization of power amplifier

Power amplifiers often exhibit undesired behavior from certain input power value which cannot be predicted with a small-signal stability analysis. Among the commonly observed undesired phenomena are spurious oscillations, frequency divisions, hysteresis or chaos. In this contribution, simulation tools are presented, enabling an in-depth study of the origin and characteristics of these phenomena. The developed global stability analysis and stabilization tools have allowed an efficient suppression of the undesired behavior in a switching-mode power amplifier, with minimum degradation of the amplifier performance, in terms of drain efficiency and output power

Fully Integrated Frequency and Phase Generation for a 6-18GHz Tunable Multi-Band Phased-Array Receiver in CMOS

Fully integrated frequency-phase generators for a 6-18GHz wide-band phased-array receiver element are presented that generate 5-7GHz and 9-12GHz first LO signals with less than -95dBc/Hz phase noise at 100kHz offset. Second LO signals with digitally controllable fourquadrant phase- and amplitude spread with better than 3° resolution are generated and allow removal of systematic reference clock skew as well as accurate selection of the received signal phase. This frequency- and phase generation scheme was successfully demonstrated in a 6-18GHz receiver system configured as an electrical 4-element array

A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS

This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from 6 to 18 GHz. The nominal conversion gain of the receiver ranges from 16 to 24 dB over the entire band while the worst-case cross-band and cross-polarization rejections are achieved 48 dB and 63 dB, respectively. Phase shifting is performed in the LO path by a digital phase rotator with the worst-case RMS phase error and amplitude variation of 0.5° and 0.4 dB, respectively, over the entire band. A four-element phased-array receiver system is implemented based on four receiver chips. The measured array patterns agree well with the theoretical ones with a peak-to-null ratio of over 21.5 dB

Global stability analysis and stabilization of a class-E/F amplifier with a distributed active transformer

Power amplifiers (PAs) often exhibit instabilities giving rise to frequency divisions or spurious oscillations. The prediction of these instabilities requires a large-signal stability analysis of the circuit. In this paper, oscillations, hysteresis, and chaotic solutions, experimentally encountered in a high-efficiency class-E/F/sub odd/ PA with four transistors combined using a distributed active transformer, are studied through the use of stability and bifurcation analysis tools. The tools have enabled an in-depth comprehension of the different phenomena, which have been observed in simulation with good agreement with experimental results. The study of the mechanism generating the instability has led to a simplified equivalent circuit from which the optimum stabilization network has been determined. The network enables a global stabilization of the circuit for all the expected operating values of the amplifier bias voltage and input power. This has been achieved with negligible degradation of the amplifier performance in terms of drain efficiency and output power. The stable behavior obtained in simulation has been experimentally confirmed